1. Field of Invention
The present invention relates to buffer circuits for digital systems, and in particular, to buffer circuits having controlled output signal switching characteristics.
2. Description of the Related Art
In many digital circuits, even within individual digital integrated circuits, it is often necessary to distribute certain signals, such as a clock signal, to many different circuits. As a result, the effective load capacitance seen by the circuit responsible for distributing the signal can become relatively high. This can often result in significant current to drive this load along with significant switching current noise (di/dt), particularly at the high signal frequencies typical to many digital circuits. Such switching current noise di/dt produces undesirable voltage spikes in circuit inductances such as integrated circuit traces and bond wires.
Accordingly, it would be desirable to have a buffer circuit for providing a buffered digital signal, such as a clock signal, in such a manner as to compensate for increased load capacitance so that the switching current noise is minimized.